Years witnessed the proliferation of a new type of CPU multi - purpose hardware accelerator containing video processing unit (Video Processing Unit - VPU). This architecture provides an alternative to the traditional approach based on the DSP that implements video processing software. At DSP system can support a wide range of video formats, increasing demand faster acdsee calculation of flows of data and video DSP adopts many to the limit. Thus, the hardware accelerating video processing units pleasing that they offer low overhead of a central processing unit (CPU - Central Processing Unit) and the lower power consumption of the system based on the DSP. Semiconductor acdsee manufacturers now want to add a third advantage, crucial: ease of use by the engineer school system. This article examines the operation and control of one of the leading accessories market, the i.MX53 from Freescale and shows how inherent characteristics make hardware application of high-quality video than ever gotten - ever. Architecture acdsee hardware accelerator hardware accelerator VPU VPU i.MX53 application processor is a typical genre in that it provides support for a wide range of video formats. These include H.264 BP / MP / HP, VC-1 SP / MP / AP, MPEG-4 SP / ASP except GMC, DivX (Xvid), MPEG-1/2, Sorenson Spark and RV-8/9 acdsee / 10. The VPU hardware can decode video (1920 1080) and encode video (1280 720). It also supports decoding and multi-media multi - sided bi - directional acdsee control it - once. Like most hardware accelerators, to i.MX53 VPU has a rich set of built-in video functions. However, unlike acdsee most hardware VPU, the i.MX53 application software easy. Providing decryption configuration / coding and the host interface, for example, is performed through the firmware in an embedded programmable DSP and called BIT processor (see Figure 1). This provides a level of flexibility and programmability unusual. And copying video data and commands acdsee into and out of what-VPU also easy because it operates on two distinct acdsee interfaces: the APB and the AXI. The channel AMBA3 APB 32-bit (32-bit) for system control and the AMBA3 AXI 64-bit for data transfer. Simple and effective control of the VPU by the host processor, the VPU provides official host interface. Most of the commands and responses between acdsee the host processor acdsee and the VPU are delivered using those impressions. Comprehensive means of control the VPU, also provided a series of API functions (Applications Programming Interface - API) that includes all necessary actions on the host CPU. However, in practice almost all functions, including rate control Flexible Macroblock Order, Arbitrary Slice Ordering, Control decoding / encoding (codec) Video and flexibility acdsee errors (error resilience), implemented the BIT processor. It means that the resources needed to host CPU to visit the VPU are limited and typically require no more than 1MIPS of processing acdsee throughput.
The components of the i.MX53 VPU i.MX53 VPU consists of two components: a video codec and VPU gasket. The video codec is the heart of the video accelerator. It consists of the BIT processor 16-bit video codec severity and the / channel interface. The VPU gasket channel responsible for making APB3 AMBA IP channel Sky Blue. The VPU can handle acdsee the four processes - temporary at best. Each process can have a different format - it can handle, for example, bit stream MPEG-4, MPEG-2, H.264 and VC-1 side by side. Decoding process consists of three functional components: Contact process: software creates and provides configuration process. Run the process: at the right time, the software will start a process. When is the right time decryption is idle and it has a bit stream decode is available in external memory. acdsee Stranded process: a process abandons software. If more than one process is ready to run, assign acdsee an identity (ID) process acdsee is different for each field from 0 to 3, using a function called RunIndex. ID allocation is based on the work order. For example, when the decoding process of MPEG-4, H.264 decoding one decoding of MPEG-2 and VC1 decoding process of running acdsee it - once, you can assign the MPEG-4 decoding key (index) Process '0 ', the decoding acdsee H.264 key process '1 ', the MPEG-2 decoding process key '2' and VC1 decoding process key '3 '. One process does not take precedence acdsee since. After creating all the processes at startup, allows the host processor to the BIT to the processes defined acdsee in RunIndex. All the processes are carried out mechanism like time division: After finishing decode process one frame, you can perform the following process. Figure 2 shows an example of such a process flow, decoding bit streams H.264 and MPEG him - once. First created and initialized two decryption processes, then each process in turn is executed with the command to "Run" (Run). Workflow in Figure 2 consists of the functions: 1. Reboot the VPU, including: Download Code BIT: BIT CPU load firmware memory. Set initial parameters: general configuration of the BIT processor, setting the base address buffer (buffer) active memory address code BIT, the bit stream buffer control and so on. Starting the run the BIT: Run the BIT processor to boot the VPU. Two. Create and format decoding: Give configuration base address acdsee and size of the bit stream acdsee buffer, the base address of the frame stores and so on. Start decoding of H.264. acdsee Do the same for the decoding of MPEG-4. Three. Run the decoding of the H.264: Give a target address configuration frame. Start the process of decoding the H.264. Wait until the BIT processor acdsee completes the process one frame. Decoded frame can be sent to the image processing unit (Image Processing Unit - IPU) of the embedded i.MX53 for further processing (post-processing) and view. Do the same for the decoding of the MPEG-4 and repeat it until all the frames are processed. Four. Stop processing: finished all the process and release all memory resources.
Crucial role of memory management memory management in VPU is crucial, because that tasks like decoding 1080i / p high bandwidth should radically. Unfortunately, often the memory bandwidth is ma
