External bus interface unit (EBIU-external bus interface unit) provides interfaces to external memo

In the 1970s and - '80 Quick designs of those involved had often limits the digital circuitry, and analog. For example, a fast parallel converters (> 10 MSPs) were available from leading manufacturers such as Analog Devices, Inc.. (ADI) since 1970. Today, high-resolution data handled higher sampling rates (eg 14 bits -> 50 MSPS) on - by analog converters - digital and digital - analog converters (ADCs and DACs) together. In addition, more and more applications require intensive algorithms to real - time. These factors require digital signal processors (DSPs) snc lavalin faster, programmers, general purpose (GP) to meet the challenges raised - by the fast data rates. Until recently, snc lavalin the majority of planners was the economy (interface) parallel converters quick to application specific integrated circuits (application-specific ICs ASICs) or systems are designed quick goals in the field (field programmable gate arrays FPGAs). These devices are able to handle many simultaneous parallel actions necessary, but they are often an - flexible and may be the most expensive. Now, with the recent launch of DSPs Blackfin , such as the ADSP-21535, was invited users to DSP vector, a programmer, general-purpose 16 - bit fixed point - a heart that reaches up to 300 MB - Run - that can handle the output of the input / output (I / O) and ongoing core data required to process the many fastest existing converters. Accordance with the core clock frequency, can achieve a maximum system clock (SCLK) of 133 MB - Run. [Do not confuse this and SCLK serial clock for the serial peripheral interface (serial peripheral interface - SPI)].
GP DSP usually costs much less than the corresponding components closest digital processing FPGAs and ASICs, and are easily programmable. In addition, because of the design cycle DSP GP are much shorter, time to market may be shorter. With FPGAs / ASICs, users must often hire or consult with professionals with expertise in design capabilities. They may also be required to send the Intellectual Property (IP intellectual property) out of their company, risking confidentiality of hardware, firmware snc lavalin and software. On the other hand, GP DSP code storage memory can be read-only memory (ROM) or disguised to DSP (such as the products of the ADSP-2153x) more protective IP. Finally, the GP DSPs are fully programmable, snc lavalin unlike ASIC applications, where each change leads to costly redesign (time and money). These factors motivated many engineers see in GP DSP solution chosen, especially when the heart rates can approach those of chips "Pentium -class." The ADSP-21535, the first ADI's Blackfin family, designed to work optimally channel environment - computer, while newer Sltcnonim appear in Kobe (within a year) will be parallel peripheral interface (PPI), designed specifically to work with the data I / O. But in the meantime, the power of the ADSP-21535 can be used in designs urgent, such as wireless applications, the - by using it along with a small amount of readily available external circuits. What are the issues? In general, snc lavalin to ensure sufficient snc lavalin width - broadband for data processing, the DSP needs a minimum clock speed of magnitude (10X) faster than the sampling rate of the converter. However, the amount of W - bandwidth snc lavalin capabilities required for processing depends on the DSP interface, themselves affected by the - by several other factors. These considerations include processing blocks versus snc lavalin processing samples, the presence of an access controller - direct memory (direct memory-access - DMA), a long memory - ports (multi-ported) and whether use of external FIFOs. Fortunately, the ADSP-21535-DMA controller has full operating independently from the core, with memories Rabbi - have level 1 (L1) and level 2 (L2). The combination of core speed, independent DMA controller and a long memory - large ports on a card (308 Kbytes), enables the ADSP-21535 to effective nodules processing high data rates. For example, if you use component connections peripheral interface (PCI-peripheral snc lavalin component interconnect) 33 MB - Hz - 32-bit snc lavalin (4-byte) Revision 2.2 compatible, (not shown in this application), you can achieve Width - Pass transferable close to -132 MB / s.
External bus interface unit (EBIU-external bus interface unit) provides interfaces to external memories asynchronous (ASYNC). If the PCI bus communication system should be used differently, snc lavalin the EBIU is only available parallel interface connecting ADSP-21535 High-speed converter. The combination of asynchronic managed control of the DSP is developed with the synchronic data stream converters may pose a particular challenge snc lavalin for the system designer. This article describes the implementation of special hardware, the low number snc lavalin of Finns, snc lavalin logic devices snc lavalin - cheap adhesive easily concepts such as chip programmable array logic (PAL), complex programmable snc lavalin logic device (CPLD) or FPGA. This logic performs the role of control between-Mixed Signal Front End (MxFE ) AD9860/AD9862 and the external memory bus of the ADSP-21535. The application is described in Figure 1 is for a mobile wireless terminal OFDM (orthogonal frequency-division multiplexed). The ADC and DAC are distributed - Time (time division multiplexed - TDM) through the interface ASYNS of the DSP (information snc lavalin presented also applies to ADCs and DACs fast parallel). You can get an engineering Record * describes the details of the interconnection scheme. It is assumed that the reader controls the information on the ADSP-21535 and -AD9860/AD9862, including the - "ADSP-2153x/ADSP21535 Blackfin DSP Hardware Reference" and a page of the AD9860/AD9862 data. You can find them on http://www.analog.com.
One goal of the early planning was to minimize the amount of external control logic required to per the DSP and converters. Guided - by the cost factor, engineers wanted to eliminate all the FIFOs in device memory or external logic. Another constraint was to avoid the routing channels of data through the logic, and thus reduce the number of pins, package snc lavalin size and cost of the logical device. Initial design shown in Figure 1